The present invention relates to semiconductor devices, and more particularly to a low-resistance, damascene T-gate metal oxide semiconductor field effect transistor (MOSFET) device. The present invention also relates to a method of fabricating a low-resistance, damascene T-gate MOSFET which uses damascene-gate processing as well as an innovative oxide removal etch.
Over the past twenty-five years or so, the primary challenge of VLSI (very large scale integration) has been the integration of an ever-increasing number of MOSFET devices with high yield and reliability. This was achieved mainly by scaling down MOSFET gate/channel length, reducing gate dielectric thickness and increasing channel doping concentration.
In conventional complementary metal oxide semiconductor (CMOS) processes, the source, drain and gate regions of the MOSFET are implanted, activated annealed and thereafter silicided so as to produce low resistance junction regions in the substrate and poly-gate lines with low-sheet resistance. For high performance 0.1 xcexcm CMOS devices, the conventional process of siliciding the poly-gates results in the following problem: For poly-gates having a width of 0.25 xcexcm or less, nucleation limited growth of the silicided polysilicon, i.e., TiSi, results in very high-sheet resistance which causes reduction in device performance.
In view of the drawback mentioned above concerning conventional CMOS processing of high-performance sub-0.1 xcexcm CMOS devices, there is a continued need for developing a new and improved method which enables the fabrication of high-performance sub-0.1 xcexcm CMOS devices without the devices having high-sheet resistance poly gates. A method is also needed which avoids poly depletion in the gate region which is adjacent to the gate dielectric.
The present invention provides a method for the fabrication of sub-0.1 xcexcm channel length CMOS devices which have very low-sheet resistance poly-gates. Moreover, the method of the present invention is capable of fabricating sub-0.1 xcexcm CMOS devices which do not exhibit any substantial loss of carriers in the area of the gate that is adjacent to the gate dielectric. That is, the method of the present invention provides sub-0.1 xcexcm CMOS devices which do not exhibit any poly depletion. A further advantage of the present invention is that the inventive method is capable of forming sub-0.1 xcexcm CMOS devices having a reduced gate resistance without increasing the device area.
The inventive method which provides the aforementioned sub-0.1 xcexcm CMOS devices utilizes a damascene-gate processing step as well as a vapor or plasma phase chemical oxide removal (COR) etch. Specifically, the method of the present invention comprises the steps of:
forming a planar structure comprising a Si-containing substrate, a sacrificial oxide layer located atop a surface of said Si-containing substrate, a patterned polysilicon region located atop a portion of said sacrificial oxide layer and a dielectric material abutting said patterned polysilicon region;
removing said patterned polysilicon region to provide an opening exposing a portion of said sacrificial oxide layer and implanting ions into said Si-containing substrate to form a device channel/body implant region, said device channel/body implant region having a length less than 0.1 xcexcm;
forming Si spacers on exposed vertical sidewalls of said dielectric material;
removing said exposed portion of sacrificial oxide layer utilizing a chemical oxide removal etch to expose a surface of said Si-containing substrate;
forming a gate dielectric on the exposed surface of said Si-containing substrate and oxidizing said Si spacers;
forming a recessed poly-gate region in said gate dielectric, said recessed poly-gate having an oxide layer on an upper surface thereof;
laterally etching said oxidized Si spacers and portions of said dielectric material which are above said recessed poly-gate to provide an area which is wider than said recessed poly-gate;
forming a gate conductor in said area and removing remaining dielectric material; and
forming nitride spacers on exposed vertical sidewalls of said recessed poly-gate that are beneath said gate conductor.
The present invention also relates to a low-resistance T-gate MOSFET device that is formed utilizing the above described method. Specifically, the low-resistance T-gate MOSFET device of the present invention comprises:
a Si-containing substrate comprising at least one device channel/body implant region separating a source region from a drain region, said at least one device channel/body implant region having a length of less than about 0.1 xcexcm;
a gate dielectric located at least atop said device channel/body implant region, said source region and said drain region;
a T-gate located atop a portion of said gate dielectric, said T-gate comprises a recessed bottom polysilicon region and an upper gate conductor region, said upper gate conductor region has a width that is greater than a width of said bottom polysilicon region; and
nitride spacers located on exposed vertical sidewalls of said bottom polysilicon region, said nitride spacers have an outer edge that is aligned with an outer edge of the upper gate conductor region.